1. Technical Field
Various embodiments of the present disclosure generally relate to nonvolatile memory devices and methods of operating the same and, more particularly, to single poly nonvolatile memory (NVM) cells, arrays thereof, and methods of operating the same.
2. Related Art
Recently, NVM devices have become very attractive as candidates for memory devices embedded in system-on-chip (SOC) packages also, referred to as SOC embedded memory devices. However, there may be some limitations in employing the NVM devices as the SOC embedded memory devices since general NVM devices are fabricated using a double poly process that is quite different from a single poly process corresponding to a standard complementary metal-oxide-semiconductor (CMOS) process used in fabrication of logic devices such as application specific integrated circuit (ASIC) devices.
Moreover, since the general NVM devices may be fabricated to have a stacked gate structure including a floating gate and a control gate electrode, complicated processes may be required to form the floating gate and the control gate electrode. In addition, since the floating gate and the control gate electrode have to be stacked, the possibility of misalignment between the floating gate and the control gate electrode may increase during some fabrication processes such as an etch process, thus reducing fabrication yield of the general NVM devices. Accordingly, there are some issues in single poly NVM devices fabricated using the standard CMOS process to realize the SOC embedded memory devices.